Changes between Version 4 and Version 5 of TeradriveHardwareNotes
- Timestamp:
- 08/04/2024 02:37:48 AM (9 months ago)
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TeradriveHardwareNotes
v4 v5 40 40 Key: X = writeable by both CPUS, M = writeable by M68K only, R = read-only, 1 = read-only, always 1, 0 = read only, always 0 41 41 42 {{{ 43 1160: XXXXXXXX 44 1161: 11111111 45 1162: 110XXXX0 46 1163: XXRRXXXX 47 1164: MXXXXXXX 48 1165: 0000RR0R 49 1166: XXXXXXX0 50 1167: 0000XXXX 51 }}} 52 53 1160: 42 1160: `XXXXXXXX` 54 43 Selects an 8 KiB page from kanji/romdisk/MD ROM (note only the upper 4 KiB of the page is visible on the MD side when MD firmware is enabled)\\ 55 44 Set to 21h when unlocking MD side and in BIOS boot\\ 56 45 Set to 0 by BIOS after initial 68K boot\\ 57 1162: 46 1161: `11111111`\\ 47 1162: `110XXXX0` 58 48 Controls address of memory window in 286 address space\\ 59 49 Effectively top byte of real mode segment address or physical address >> 12\\ … … 61 51 Set to CE if value in CMOS is invalid\\ 62 52 Window is 8KiB in size and is used for both PC-side access to MD hardware and the Kanji/romdisk ROM\\ 63 1163: 53 1163: `XXRRXXXX` 64 54 bit 0: Enables auxilliary ROM on 68K side\\ 65 55 bit 1: Enable 286 memory window into 68K addres space (must be clear when booting 68K)\\ 56 bit 2: unknown\\ 57 bit 3: unknown\\ 58 bit 4: Returns value written by 68K to AE0001 bit 0\\ 59 bit 5: Returns value written by 68K to AE0001 bit 1\\ 60 bit 6: Value written here is readable by 68K at AE0001 bit 2\\ 61 bit 7: Value written here is readable by 68K at AE0001 bit 3\\ 66 62 Set to 1 by BIOS and during MD unlock procedure\\ 67 63 1164: `MXXXXXXX` 64 bit 0: Setting bit from 286 side pauses the 286 and releases 68K from reset\\ 65 Clearing bit from 68K side puts 68K into reset and releases 286\\ 66 Making certain other reg changes seems to make clearing this bit have no effect\\ 67 bit 1: 0 = Tera drive boot ROM mapped at 0 on 68K, 1 = cart mapped at 0\\ 68 bit 2: Controls video switch - 0 = PC video, 1 = MD video\\ 69 bit 3: Dual boot bit. When both this and bit 1 are set, bit 0 is ignored and both CPUs run independently.\\ 70 bit 4: Unclear function. When set bits 4 & 5 become 10 in AE0003 and 1165 returns a fixed sequence (D5,7F,00,AA,55,FF,80,2A)\\ 71 bit 5: Unknown\\ 72 bit 6: Set on TMSS failure immediately before wedging 68K by reading from VDP while configured for writes\\ 73 bit 7: Seems to start as 1, clearable on 68K but not on 286\\ 74 1165: `0000RR0R` 75 bit 0: Indicates PC/MD switch setting, 0 = MD boot, 1 = PC boot\\ 76 bit 2: Indicates video switch setting, 0 = "Video", 1 = "RGB"\\ 77 bit 3: 1 indicates bus timeout on 286 access to 68K bus, cleared on read\\ 78 bit 5: indicates MD hardware has been "unlocked" ('SEGA' has been written to $A14000)\\ 79 1166: `XXXXXXX0` 80 low bits of selected 8K page for access to 68K memory from 286\\ 81 1167: `0000XXXX` 82 high bits of selected 8K page for acces to 68K memory form 286\\ 83 when taken together with 1166, holds `68K address >> 12`\\ 84 Also used along with 1166 for passing params from PC side to MD-side firmware\\ 68 85 69 86 == IC List
